1 data sheet acquired from harris semiconductor schs147a features ? select one of eight data outputs active low for 138, active high for 238 ? l/o port or memory selector ? three enable inputs to simplify cascading ? typical propagation delay of 13ns at v cc = 5v, c l = 15pf, t a = 25 o c ? fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads ? wide operating temperature range . . . -55 o c to 125 o c ? balanced propagation delay and transition times ? signi?cant power reduction compared to lsttl logic ics ? hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v ? hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 m a at v ol , v oh pinout cd74hc138, cd74hct138, cd74hc238, cd74hct238 (pdip, soic) top view signal names in parentheses are for hc238 and hct238. 14 15 16 9 13 12 11 10 1 2 3 4 5 7 6 8 a0 a1 a2 e1 e2 e3 gnd ( y7) y7 v cc y1 ( y1) y2 ( y2) y3 ( y3) y4 ( y4) y5 ( y5) y6 ( y6) y0 ( y0) october 1997 - revised february 1999 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright ? 1999, texas instruments incorporated cd74hc138, cd74hct138, cd74hc238, cd74hct238 high speed cmos logic 3-to-8 line decoder/ demultiplexer inverting and non-inverting [ /title (cd74 hc138 , cd74 hct13 8, cd74 hc238 , cd74 hct23 8) / sub- j ect (high speed
2 description the harris cd74hc138, cd74hc238 and cd74hct138, cd74hct238 are high speed silicon gate cmos decoders well suited to memory address decoding or data routing applications. both circuits feature low power consumption usually associated with cmos circuitry, yet have speeds comparable to low power schottky ttl logic. both circuits have three binary select inputs (a0, a1 and a2). if the device is enabled, these inputs determine which one of the eight normally high outputs of the hc/hct138 series will go low or which of the normally low outputs of the hc/hct238 series will go high. two active low and one active high enables ( e1, e2, and e3) are provided to ease the cascading of decoders. the decoders 8 outputs can drive 10 low power schottky ttl equivalent loads. functional diagram ordering information part number temp. range ( o c) package pkg. no. cd74hc138e -55 to 125 16 ld pdip e16.3 cd74hct138e -55 to 125 16 ld pdip e16.3 cd74hc238e -55 to 125 16 ld pdip e16.3 cd74hct238e -55 to 125 16 ld pdip e16.3 cd74hc138m -55 to 125 16 ld soic m16.15 cd74hct138m -55 to 125 16 ld soic m16.15 cd74hc238m -55 to 125 16 ld soic m16.15 cd74hct238m -55 to 125 16 ld soic m16.15 cd74hc138sm -55 to 125 16 ld ssop m16.209 notes: 1. when ordering, use the entire part number. add the suf?x 96 to obtain the variant in the tape and reel. 2. wafer and die for this part number is available which meets all electrical specifications. please contact your local sales office or harris customer service for ordering information. ordering information part number temp. range ( o c) package pkg. no. truth table cd74hc138, cd74hct138 inputs outputs enable address e3 e2 e1 a2 a1 a0 y0 y1 y2 y3 y4 y5 y6 y7 xxhxxxhhhhhhhh lxxxxxhhhhhhhh xhxxxxhhhhhhhh hllllllhhhhhhh hllllhhlhhhhhh hlllhlhhlhhhhh hl l lhhhhhlhhhh 15 14 13 12 10 7 9 11 1 2 3 5 6 4 e3 e2 e1 a2 a1 a0 y0 y7 y6 y5 y4 y3 y2 y1 y0 y7 y6 y5 y4 y3 y2 y1 hc/hct 238 hc/hct 138 cd74hc138, cd74hct138, cd74hc238, cd74hct238
3 hllhllhhhhlhhh hllhlhhhhhhlhh hllhhlhhhhhhlh hllhhhhhhhhhhl note: h = high voltage level, l = low voltage level, x = dont care truth table cd74hc238, cd74hct238 inputs outputs enable address e3 e2 e1 a2 a1 a0 y0 y1 y2 y3 y4 y5 y6 y7 xxhxxxllllllll lxxxxxl l l l l l l l xhxxxxllllllll hlllllhlllllll hllllhlhllllll hlllhlllhlllll hlllhhlllhllll hllhllllllhlll hllhlhlllllhll hllhhlllllllhl hllhhhlllllllh note: h = high voltage level, l = low voltage level, x = dont care truth table cd74hc138, cd74hct138 inputs outputs enable address e3 e2 e1 a2 a1 a0 y0 y1 y2 y3 y4 y5 y6 y7 cd74hc138, cd74hct138, cd74hc238, cd74hct238
4 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 3) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 ssop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?cation is not im plied. note: 3. q ja is measured with the component mounted on an evaluation pc board in free air. dc electrical speci?cations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o cto125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads - - --- - - - - v -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads - - --- - - - - v 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 m a cd74hc138, cd74hct138, cd74hc238, cd74hct238
5 hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc and gnd 0 5.5 - 0.1 - 1- 1 m a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 m a additional quiescent device current per input pin: 1 unit load (note 4) d i cc v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 m a note: 4. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?cations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o cto125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads a0-a2 1.5 e1, e2 1.25 e3 1 note: unit load is d i cc limit speci?ed in dc electrical table, e.g., 360 m a max at 25 o c. switching speci?cations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max hc types propagation delay t plh, t phl c l = 50pf 2 - - 150 - 190 - 225 ns address to output 4.5 - - 30 - 38 - 45 ns c l = 15pf 5 - 13 - - - - - ns c l = 50pf 6 - - 26 - 33 - 38 ns cd74hc138, cd74hct138, cd74hc238, cd74hct238
6 enable to output hc/hct138 t plh, t phl c l = 50pf 2 - - 150 - 190 - 265 ns 4.5 - - 30 - 38 - 53 ns 6 - - 26 - 33 - 45 ns output transition time (figure 1) t tlh , t thl c l = 50pf 2 - - 75 - 95 - 110 ns 4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns power dissipation capacitance, (notes 5, 6) c pd c l = 15pf 5 - 67 - - - - - pf input capacitance c in - - - - 10 - 10 - 10 pf hct types propagation delay address to output t plh , t phl c l = 50pf 4.5 - - 35 - 44 - 53 ns c l = 15pf 5 - 14 - - - - - ns enable to output hc/hct138 t plh , t phl c l = 50pf 4.5 - - 35 - 44 - 53 ns enable to output hc/hct238 t plh, t phl c l = 15pf 4.5 - - 40 - 50 - 60 ns output transition time (figure 2) t tlh , t thl c l = 50pf 4.5 - - 15 - 19 - 22 ns power dissipation capacitance, (notes 5, 6) c pd c l = 15pf 5 - 67 - - - - - pf input capacitance c in - - - - 10 - 10 - 10 pf notes: 5. c pd is used to determine the dynamic power consumption, per gate. 6. p d = v cc 2 f i (c pd + c l ) where: f i = input frequency, c l = output load capacitance, v cc = supply voltage. switching speci?cations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min typ max min max min max test circuits and waveforms figure 7. hc and hcu transition times and propaga- tion delay times, combination logic figure 8. hct transition times and propagation delay times, combination logic t phl t plh t thl t tlh 90% 50% 10% 50% 10% inverting output input gnd v cc t r = 6ns t f = 6ns 90% t phl t plh t thl t tlh 2.7v 1.3v 0.3v 1.3v 10% inverting output input gnd 3v t r = 6ns t f = 6ns 90%
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 1999, texas instruments incorporated
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